1. Field of the Invention
The present invention relates to a dielectric layer structure and manufacturing method thereof, and more particularly, to a dielectric layer structure having superior process control and stability and manufacturing method thereof.
2. Description of the Prior Art
Devices in semiconductor industry need to undergo several complicated processes such as photolithograph process, dry or wet etching process, ion implantation, and heat treatment, etc. to construct precise integrated circuits in layers. Among those complicated processes, the process control of dielectric layer etching has become a critical factor, particularly in some application such as damascene process or interconnection technique. For example, in a damascene process, a dielectric layer is etched to form patterns comprising trenches or via. Then the trenches or via are filled with copper, and a planarization process is performed to complete formation of damascene structure. Additionally, to satisfy requirements of low RC delay effects, low-K material, ultra low-k (ULK) material, or porous low-k material is used to be the dielectric layer in the damascene structure.
Please refer to FIGS. 1-5, which are schematic drawings of a conventional trench-first dual damascene process. As shown in FIG. 1, a substrate 10 having at least a conductive layer 12 and a base layer 14 comprising silicon nitride sequentially formed thereon is provided. And a dielectric layer 16, a cap layer 18, a metal hard mask layer 20, and a bottom anti-reflective coating (BARC) layer 22 are sequentially formed on the base layer 14. Then, a photoresist layer 30 is formed and patterned to form an opening 32 by a well-known photolithography method. The opening 32 is used to define a trench pattern of a damascene structure.
Please refer to FIGS. 1 and 2. Subsequently, an etching process is performed. Accordingly a trench recess 34 is etched into the metal hard mask layer 20 and the cap layer 18 through the opening 32. The etching is stopped on the cap layer 18. The remaining photoresist layer 30 and the BARC layer 22 are then stripped off.
As shown in FIG. 3, another BARC layer 36 is deposited over the substrate 10 and fills the trench recess 34. And another photoresist layer 40 is formed on the BARC layer 36. The photoresist layer 40 has an opening 42 patterned by a conventional photolithography method. The opening 42 is situated directly above the trench recess 34 and the conductive layer 12, and is used to define a via pattern of a damascene structure. As shown in FIG. 4, the BARC layer 36, the cap layer 18, and the dielectric layer 16 are etched through the opening 42 with the photoresist layer 40 being an etching mask. Thus, a partial via feature 44 is formed in an upper portion of the dielectric layer 16. Then the remaining photoresist layer 40 and the BARC layer 36 are stripped off by an oxygen plasma.
Please refer to FIG. 5. Next, the metal hard mask layer 20 serves as an etching hard mask in an etching process, which is performed to etch away the cap layer 18 and the dielectric layer 16 through the trench recess 34 and the partial via 44, thereby a dual damascene pattern comprising a trench opening 52 and a via opening 54 is obtained. Then, the damascene pattern is filled with a conductive metal such as copper followed by a planarization process that is performed, thus a dual damascene structure is formed. It is noteworthy that the dielectric layer 16 possesses a low mechanical strength and a compressive stress which leads to line distortion occurring in the dielectric layer 16.
Furthermore, there is another phenomenon drawing attention in the conventional damascene formation process: Generally, the cap layer 18 is a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) based silicon oxide layer with TEOS used as a precursor. Because the TEOS layer comprises lots of Si—OH bonds and Si—H dangling bonds, the TEOS layer is a hydrophilic layer which is apt to absorb moisture. And the absorbed moisture is then desported from the TEOS layer and into the dielectric layer 16 in following process, thus Kelvin via open are formed in the dielectric layer 16. Kelvin via open reduces reliability of the process and influences electrical performance of the damascene interconnects formed following.
To solve the problem mentioned above, those skilled in the art provide many approaches, for example, a multi-layered cap layer such as a tri-layered cap layer is provided. The tri-layered cap layer provides a tensile stress layer offering a tensile stress which is opposite to the compressive stress of the dielectric layer. The multi-layered cap layer also provides hermetical layers sandwiching the tensile stress layer to prevent the tri-layered cap layer itself from absorbing the moisture and to prevent the dielectric layer from the desported moisture. However, due to the multi-layered characteristic, the process for the multi-layered cap layer has inferior process control, for example, it is not easy to form openings or recesses in the multi-layered cap layer. And The multi-layered cap layer also has inferior process stability. Therefore, a simple layer capable of balancing stress in the dielectric layer and preventing itself from absorbing moisture is needed.